I Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and, more particularly, to a method of manufacturing a MES FET which uses a compound semiconductor such as GaAs as a substrate.
II Description of the Prior Art
The following two methods of manufacturing, by self-alignment, a Schottky gate-type field effect transistor (to be referred to as MES FET hereinafter) having a semi-insulating semiconductor substrate of GaAs or the like, are conventionally known:
(1) A method of forming a source region and a drain region by self-alignment with respect to a gate electrode; and
(2) A method of forming a source electrode and a drain electrode by self alignment with respect to a gate electrode.
Method (1) will be described with reference to FIGS. 1A to 1D. An n-type impurity such as Si is diffused in a semiconductor substrate 1 of GaAs to form a low impurity concentration region 1a, as shown in FIG. 1A. Thereafter, a gate electrode 2 of a high melting metal such as a TiW alloy is formed on the region la. As shown in FIG. 1B, a plasma silicon oxide film (to be referred to as P-SiO.sub.2 film hereinafter) 3 is deposited by plasma CVD on surfaces of the electrode 2 and the substrate 1. A resist film 4 is formed on the film 3 and selectively etched to form an opening at the position corresponding to the region 1a. A donor impurity such as Si is ion-implanted in the substrate 1 through the film 3 exposed in the resist opening. In this case, the electrode 2, a portion of the film 3 at side surfaces of the electrode 2, and the film 4 serve as a mask for ion implantation. In this manner, two high impurity concentration regions 1b are formed, by self-alignment, at positions in the substrate 1 corresponding to the two sides of the electrode 2, with respect to the electrode 2. At the same time, a region 1a, having a length slightly larger than the gate length of the electrode 2, is left immediately thereunder. Then, the film 4 is removed and annealing is performed to activate ions implanted in the regions 1b.
Subsequently, a resist pattern 5 is formed on the film 3, as shown in FIG. 1C. Thereafter, the film 3 on the regions 1b is selectively etched by using the pattern 5 as a mask. An ohmic metal film 6 which can ohmic-contact with the substrate is deposited on the entire surface of the substrate so that it is deposited on the pattern 5 and the regions 1b in the openings of the film 3.
When the pattern 5 is removed, by the lift-off method, together with its overlying film 6 from the film 3, portions of the film 6 deposited on the two regions 1b are left, as shown in FIG. 1D, as a drain electrode 7 and a source electrode 8.
Therefore, according to the method (1), the source and drain regions are formed by self alignment with respect to the gate electrode.
Method (2) will be described with reference to the accompanying drawings FIGS. 2A to 2F. An n-type impurity such as Si is diffused in a semiconductor substrate 1 such as GaAs to form a low impurity concentration region 1a, as shown in FIG. 2A. Thereafter, a gate electrode 2 consisting of a low resistance metal is formed by the lift-off method at substantially a central portion of the region 1a. Subsequently, an insulating film (SiO.sub.2 film) 9 is deposited by thermal CVD on the entire surface of the obtained structure, as shown in FIG. 2B. Then, anisotropic etching such as reactive ion etching (to be referred to as RIE) is performed so that the film 9 is left only on side surfaces of the electrode 2, as shown in FIG. 2C. An ohmic metal film 10 is deposited on the entire surface of the obtained structure, as shown in FIG. 2D. At the same time, a substantially flat resist film 11 is formed on the film 10. Then, in accordance with a combination of anisotropic etching and ion milling, the film 10 on the electrode 2 is levelled through selective etching in order to form a source electrode and a drain electrode as shown in FIG. 2E. When the flat film 11, left after the etching, is removed, the structure shown in FIG. 2F can be obtained. Description of steps following FIG. 2F are omitted. According to the method (2) described with respect to FIGS. 2A to 2F, distances between the electrode 2 and the source and drain electrodes are determined by self-alignment in accordance with the thickness of the film 9 deposited on the side surfaces of the electrode 2. Therefore, mask misalignment in a lithographic step does not occur, so that the distances between the gate electrode and the source and drain electrodes can be precisely controlled.
According to the method (1) described with reference to FIGS. 1A to 1D, the source and drain regions are formed by self-alignment with respect to the gate electrode. However, the source and drain electrode must be formed in accordance with a conventional, photoetching process which uses a photomask. Therefore, the source and drain electrodes cannot be formed by self-alignment. As a result, distances between the gate and the source and drain tend to vary due to mask misalignment. In a GaAs MES FET, the distance between the gate and source influences the resistance of a source series resistor, which in turn influences characteristics of the GaAs MES FET. With method (1), which cannot precisely control the distance between the gate electrode and the drain electrode, a uniform GaAs MES FET having good characteristics cannot be obtained.
Meanwhile, according to method (2), described with respect to FIGS. 2A to 2F, problems inherent in method (1) are solved. However, in this case, since both RIE and ion milling are used in the step for separating the source and drain electrodes, the manufacturing process becomes complex. In addition, when etching is performed on the entire surface of the obtained structure, as shown in FIG. 2E, it is difficult both to determine the time at which etching will end and to separate the source and drain uniformly with respect to all elements in a wafer.